Synchronization Stability of Inverter Based Resources during Faults on Low Voltage Grids
Author
Bhatnagar, Kaustubh
Term
4. term
Education
Publication year
2022
Submitted on
2022-05-30
Pages
85
Abstract
Dette speciale undersøger, hvordan inverterbaserede ressourcer kan forblive synkroniseret med lavspændingsnettet under kortslutningsfejl, i takt med at elsystemet bliver mere kraftelektronikdomineret og underlagt skærpede FRT-krav. Problemet adresseres for både symmetriske fejl, hvor tab af synkronisering kan opstå afhængigt af netimpedansen og strøminjektionens vinkel, og asymmetriske fejl, der giver 2. harmoniske svingninger og risiko for overspænding i ikke-fejlramte faser. Specialet udleder aktive og reaktive strømoverførselsgrænser som funktion af netimpedans og strøminjektionsvinkel for at undgå tab af synkronisering under symmetriske fejl. Der foreslås desuden en modificeret, fleksibel positiv/negativ-sekvensinjektion, som inddrager DC-link-dynamik, undgår kompleks sekvensekstraktion med PLL og har lav beregningsbyrde; metoden sigter mod at dæmpe 2. harmoniske svingninger og undgå overspænding i ikke-fejlramte faser under asymmetriske fejl. Metoden vurderes gennem tidsdomæneanalyser på en lavspændingsnet-case og realtidsafprøvning via hardware-in-the-loop, med fokus på enkle kontrolstrategier, der er anvendelige i lavspændingsnet.
This thesis investigates how inverter-based resources can remain synchronized with low-voltage grids during short-circuit faults as power systems transition toward power-electronics dominance and face stricter fault ride-through (FRT) requirements. The study addresses both symmetrical faults, where loss of synchronism depends on line impedance and current injection angle, and asymmetrical faults, which introduce second-harmonic oscillations and risk of overvoltage in non-faulted phases. It derives active and reactive current transfer limits as functions of line impedance and injection angle to prevent loss of synchronism during symmetrical faults. In addition, it proposes a modified, flexible positive/negative sequence current injection that accounts for DC-link dynamics, avoids complex PLL-based sequence extraction, and has low computational burden; the method aims to attenuate second-harmonic oscillations and prevent overvoltage in non-faulted phases during asymmetrical faults. The approach is evaluated through time-domain studies on a low-voltage case and real-time hardware-in-the-loop implementation, emphasizing simple control strategies suitable for low-voltage grids.
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