Implementation of a LTE inspired Transceiver on a USRP Platform
Translated title
Implementation af en LTE inspireret sender/modtager på en USRP platform
Authors
Buthler, Jakob Lindbjerg ; Buhl, Michael
Term
10. term
Publication year
2012
Submitted on
2012-05-31
Pages
133
Abstract
Long Term Evolution (LTE) er en mobilstandard med op til 300 Mbit/s. Vi bruger LTE som reference for at undersøge, hvilke funktioner i det fysiske lag i et højtydende kommunikationssystem der med fordel kan hardwareaccelereres. Vi analyserer CRC (fejlkontrol), Turbo-kodning/-dekodning (fejlrettelse), OFDM (modulation, der fordeler data på mange bærefrekvenser) samt kanalequalizere som ZF, MMSE og Turbo-equalisering, der afbøder kanalens forvrængninger. Til implementering peger vi på USRP2-platformen, fordi den har flere RF-frontends og et eksisterende FPGA-design, som allerede udfører indledende RF-databehandling som nedsampling og filtrering. Ved at sammenligne ydeevne på CPU og FPGA finder vi, at især OFDM og Turbo-dekoderen får markant gavn af hardwareacceleration. Den første praktiske indsats fokuserer derfor på OFDM, realiseret som transparente, genbrugelige moduler. OFDM's kerneoperation, FFT (fast Fourier-transform), er grundigt undersøgt og kræver ikke ekstra kommunikation mellem Host-PC og USRP ud over den eksisterende. For at forbinde FFT'ens blokvise behandling med FPGA'ens kontinuerte datastrøm konstruerer vi et pipeline-modul, der samler symboler i pakker.
Long Term Evolution (LTE) is a mobile communication standard promising up to 300 Mbps. We use LTE as a reference case to examine which physical-layer functions in a high-performance communication system are worth moving from software to hardware. We study CRC (error checking), Turbo coding/decoding (error correction), OFDM (a modulation that spreads data across many subcarriers), and channel equalizers such as ZF, MMSE, and Turbo equalization that mitigate distortions introduced by the channel. For implementation, we point to the USRP2 platform because it offers multiple RF front-ends and an existing FPGA design that already handles early RF data processing like down-sampling and filtering. By comparing performance on a CPU and on an FPGA, we find that OFDM and especially the Turbo decoder benefit significantly from hardware acceleration. Our initial implementation effort therefore focuses on OFDM, built as transparent, reusable modules. The core operation of OFDM, the FFT (fast Fourier transform), is well understood and does not require additional communication between the Host-PC and the USRP beyond what already exists. To bridge the FFT's block-based processing and the FPGA's continuous data stream, we design a pipeline module that collects symbols into packets.
[This abstract was generated with the help of AI]
Keywords
OFDM ; USRP ; LTE ; Turbo codes ; HW acceleration ; FPGA
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