Feed-Forward Quadrature Phase Shift Keying Frequency Offset Correction: The development of a hardware-implementable phase error estimator algorithm for use in third generation mobile telephony systems
Authors
Hansen, Karl Damkjær ; Jakobsen, Kasper Lund
Term
10. term
Education
Publication year
2010
Submitted on
2010-06-03
Pages
116
Abstract
Projektet udvikler, analyserer og implementerer en algoritme, der kompenserer for frekvensdrift i 3G-transceivere—små forskydninger i bærefrekvensen, som kan forringe kommunikationen markant. Tre kandidatalgoritmer blev vurderet; én blev valgt. Den kombinerer en faseestimator, der gennemsnitliggør tidligere fasefejl i en filterstruktur, og en fasehopdetektor, der fjerner tvetydigheder skabt af denne udglatning. Den oprindelige metode var designet til BPSK (Binary Phase Shift Keying), men da 3G bruger QPSK (Quadrature Phase Shift Keying), blev algoritmen udvidet. Den udvidede version blev simuleret og vurderet med fastpunktaritmetik og kompleks talrepræsentation. Simulationerne viser, at ydelsen konvergerer mod den teoretiske QPSK-ydelse uden frekvensdrift. Algoritmens kompleksitet blev brugt til at vælge en egnet platform. Designet blev opdelt i pipeline-trin, og den indbyggede parallelisme blev udnyttet for at minimere køretiden. Den valgte platform var en Altera Cyclone 3 FPGA. Et testsystem og algoritmen blev implementeret på FPGA’en, og den målte ydelse lignede tæt MATLAB-simulationerne. Algoritmen vurderes derfor som fungerende og egnet til prototypebrug i 3G-transceiversystemer.
This project develops, analyzes, and implements an algorithm to compensate for frequency drift in 3G wireless transceivers—small shifts in the carrier frequency that can significantly degrade communication. Three candidate algorithms were reviewed; one was selected. It combines a phase estimator that averages past phase errors using a filter and a phase-jump detector that removes ambiguities introduced by that averaging. The original method was designed for BPSK (Binary Phase Shift Keying), but because 3G uses QPSK (Quadrature Phase Shift Keying), the algorithm was extended accordingly. The extended version was simulated and evaluated using fixed-point arithmetic and complex-number representation. The simulations show that its performance converges toward the theoretical QPSK performance without frequency drift. Algorithm complexity was used to choose a suitable platform. The design was arranged in pipeline stages, and its inherent parallelism was exploited to minimize execution time. The chosen platform was an Altera Cyclone 3 FPGA. A test system and the algorithm were implemented on the FPGA, and the measured performance closely matched MATLAB simulations. The algorithm is therefore considered working and suitable for prototype use in 3G transceiver systems.
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