A Generalized Double Pulse Test With Potential Short Circuit Protection For SiC-MOSFET's

Peters, Steffen

4. term

Energy Engineering, Master

2023

59

This thesis investigates and implements a generalized double pulse test (DPT) to characterize the switching losses of SiC MOSFETs. The approach establishes target test points by designing an inductor and capacitor so that specified current and voltage are reached within a defined time window. In a laboratory setup, device voltage and current during turn‑on and turn‑off are measured and integrated to obtain switching energy. The DPT is modeled in LTspice—first ideally and then with non‑ideal and parasitic elements—and simulated waveforms and loss calculations are compared with laboratory measurements, including tests at different gate resistances and operating points, to assess generality. The study also explores short‑circuit behavior in a DPT and evaluates prospective protection methods; simulations indicate that a crowbar arrangement can divert fault energy and protect the device under test. Overall, the work shows that the proposed generalized DPT enables extraction of switching losses across varying conditions and that crowbar‑based protection is a promising option for safeguarding SiC MOSFETs during testing.

Dette speciale undersøger og implementerer en generaliseret double pulse test (DPT) til karakterisering af koblingstab i SiC‑MOSFET’er. Metoden fastlægger ønskede testpunkter ved at designe en induktor og en kondensator, så specificeret strøm og spænding opnås inden for et givent tidsvindue. I en laboratorieopstilling måles komponentens spænding og strøm under ind- og udkobling og integreres til koblingsenergi. DPT’en modelleres i LTspice – først ideelt og derefter med ikke‑ideelle og parasitiske elementer – og de simulerede bølgeformer og tabsberegninger sammenlignes med laboratoriemålinger for at vurdere overensstemmelse og generalitet, herunder forsøg ved forskellige gate‑modstande og driftsbetingelser. Specialet undersøger også kortslutningsforløb i en DPT og vurderer mulig beskyttelse; simuleringer indikerer, at en crowbar‑løsning kan aflede fejleffekt og beskytte den testede enhed. Samlet set viser arbejdet, at den foreslåede generaliserede DPT muliggør udtræk af koblingstab under varierende betingelser, og at crowbar‑baseret beskyttelse er en lovende mulighed for at sikre SiC‑MOSFET’er under test.

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