Design and Implementation of a Novel Dataflow Model and an Intermediate Representation Language for High Level Synthesis on Field Programmable Gate Arrays
Author
Johansen, Jeppe
Term
10. term
Education
Publication year
2012
Submitted on
2012-12-03
Abstract
Field Programmable Gate Arrays (FPGA’er) muliggør massiv parallel databehandling, men udnyttelsen begrænses ofte af programmeringsværktøjer og designmetoder på højt niveau. Dette arbejde undersøger eksisterende høj-niveau-sprogs tilgange (bl.a. FPGA-Oberon, CAL og Vivado HLS) samt decoupled access/execute-arkitekturer for at identificere styrker og svagheder. På den baggrund foreslås en ny dataflow-model, der samler de gode egenskaber, samt et høj-niveau mellemliggende repræsentationssprog (IR) til effektivt at udtrykke dataflowet. Der præsenteres også en række heuristikker, der skal lette optimering af den genererede FPGA-implementering. En compiler er implementeret, som oversætter IR til Verilog HDL og udfører bl.a. konstantpropagering, forenkling, fjernelse af ubrugt kode, indsættelse af løbetællere og bitbreddeanalyse. Den resulterende dataflow-model er enkel og velegnet til komplekse algoritmer inden for digital signalbehandling. I en test med et FIR-filter sammenlignes løsningen med en anden HLS-implementering: udførelseshastigheden er lidt lavere, mens arealforbruget er på niveau; den større fleksibilitet øger transportoverhead, men giver også markant større udtrykskraft.
Field Programmable Gate Arrays (FPGAs) enable massive parallel data processing, yet their potential is often limited by high-level programming tools and design methodologies. This thesis reviews existing high-level approaches (including FPGA-Oberon, CAL, and Vivado HLS) and decoupled access/execute architectures to identify strengths and limitations. Building on this, it proposes a new dataflow model that combines favorable features and introduces a high-level intermediate representation (IR) language to express the dataflow effectively. A set of heuristics is presented to facilitate optimization of the synthesized FPGA design. A compiler is implemented that translates the IR to Verilog HDL and performs constant propagation, operation simplification, dead-code removal, loop counter insertion, and bit-width analysis. The resulting dataflow model is simple and well suited to complex digital signal processing algorithms. In a FIR filter case study, the approach is compared with another high-level synthesis language: overall execution speed is slightly lower while area usage is comparable; the added flexibility increases transport overhead but substantially improves expressiveness.
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