Concept Development for the Next Generation of Metal Detectors

Bjerrum, Bo ; Kristiansen, Klaus Dahl

10. term

Elektronik og IT, Kandidatuddannelsen (Spec. Applied Signal Processing and Implementation)

2008

207

This thesis explores whether a digital, FPGA-based metal detector can serve as the next generation of metal detection, especially in product environments such as food processing. The work begins by developing a mathematical model of a three-coil detector head based on Maxwell’s equations and frequency-dependent permeability, which is validated against measurements to confirm agreement between theory and practice. The model supports signal analysis that extracts amplitude and phase features to distinguish metal from product, showing dependence on object size and frequency so the operating frequency can be chosen product-optimally. Building on this, detection and classification methods are developed and analyzed (including DFT-based preprocessing and LRAD, covariance, and Bayes classifiers) and implemented algorithmically in VHDL and Quartus as a digital FPGA solution. The system is specified, designed, and integrated in a HW/SW platform, and evaluation demonstrates detection of an iron sphere at 0.58% of the detector head opening, indicating the concept’s practical viability.

Dette speciale undersøger, om en digital, FPGA-baseret metaldetektor kan udgøre næste generation af metaldetektion, særligt i miljøer med fødevarer. Arbejdet starter med at udvikle en matematisk model af et tre-spole detektorhoved baseret på Maxwell’s ligninger og frekvensafhængig permeabilitet, som valideres mod målinger for at bekræfte sammenhængen mellem teori og praksis. Modellen bruges til signalanalyse, hvor amplitude- og faseegenskaber udtrækkes til at skelne metal fra produkt, og det vises, at værdierne afhænger af både objektstørrelse og frekvens, så frekvensen kan vælges produktoptimalt. På denne baggrund udvikles og analyseres metoder til detektion og klassifikation (bl.a. DFT-baseret forbehandling samt LRAD-, kovarians- og Bayes-klassifikatorer), som implementeres algoritmisk i VHDL og Quartus som en digital løsning på FPGA. Systemet specificeres, designes og integreres i en HW/SW-platform, og evaluering viser, at en jernkugle på 0,58 % af detektorhovedets åbning kan detekteres, hvilket dokumenterer, at konceptet er anvendeligt.

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