A Benchmarking Tool for Evaluation of Approximate Arithmetic Circuits in Convolutional Neural Networks
Authors
Term
4. semester
Education
Publication year
2024
Submitted on
2024-05-31
Pages
219
Abstract
The contents of this thesis describes the development of a benchmarking tool capable of taking an approximate, combinatorial arithmetic circuit and analysing the power consumption, latency, error characteristics, and implications of implementation on a given CNN. The purpose of the tool is to bridge the gap between approximate computing and machine learning, leveraging the reduction in power consumption and latency, in an attempt to make machine learning more sustainable. The benchmarking tool is structured in three steps. In step I, the arithmetic circuit is synthesised and the netlist is used to count the logic gates and their type, and by extension estimate the total amount of transistors required for the circuit. The netlist is also used to find the latency of the circuit by converting the netlist to a directed acyclic graph and searching for the path that results in the longest propagation delay. In step II the circuit is applied to a small-scale custom CNN implemented in C++. The error characteristics are generalised in easily scalable custom CNN layers, and the C++ model is utilised to evaluate the ‘‘appropriateness’’ of the generalisation. Lastly, in step III the custom layers are used in a full-scale CNN, whereby the implications on the accuracy can be weighed against the drop in power consumption and latency. The custom layers were applied in a full-scale example CNN, where the potential of approximate hardware was highlighted: The accuracy reduced form ∼ 70 % to ∼ 60 %, however, with an optimistic estimate the power consumption dropped to 10.3 % and the latency dropped to below half.
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