Turbo Coding: Hardware Acceleration of an EGPRS-2 Turbo Decoder on an FPGA

Student thesis: Master thesis (including HD thesis)

  • Jesper Kjeldsen
This report presents a hardware implementation of an EGPRS-2 turbo decoder algorithm called soft-output Viterbi algorithm (SOVA), where techniques for optimizing the implementation has been used to establish an Finite State Machine with Datapath (FSMD) design. The report is developed in cooperation with Rohde \& Schwarz Technology Center A/S (R\&S). EGPRS-2 is the second evolution of GPRS, a standard for wireless transmission of data over the most widespread mobile communication network in the world, GSM. The technologies utilized by EGPRS-2 to improve Quality of Service is investigated in this report to determine an application with high complexity. Turbo coding is chosen and its encoder and decoder structures are analyzed. Based on the interest of R\&S, a SOVA implemented in Matlab is analyzed and through profiling a bottleneck, that takes up 70 \% of the decoders execution time, is found. This bottleneck is mapped to an FSMD implementation, where the datapath is determined through cost optimization techniques and a pipeline is also implemented. XILINX Virtex-5 is used as an implementation reference to estimate a decreased execution time of the hardware design. It shows that a factor 1277 improvement over the Matlab implementation can be achieved and that it is able to handle the maximum EGPRS-2 throughput speed of 2 Mbit/s.
Publication date2009
Publishing institutionAalborg University, ASPI
ID: 17741200