Intelligent IP Camera: An FPGA Motion Detection Implementation

Student thesis: Master Thesis and HD Thesis

  • Nicolas Cothereau
  • Delaite Guillaume
  • Edouard Gourdin
2. term, Computer Science, Master (Master Programme)
This Report deals with an intelligent camera implementation. This camera is linked with a Altera Field Programmable Gate Array (FPGA) platform on a DE2 Board where a motion detection algorithm is implemented. The main goal of this project is to analyse the feasibility of optimizing video surveillance with an FPGA. The aim is therefore to create a prototype to do several function, with some requirements. A room is monitored and the video captured by the camera sensor is displayed on a VGA screen. The video is recorded only when motions are detected. Then, the video is stored on a SD-Card and accessible on an Ethernet network. Hardware and software co-design is studied to implement the motion detection algorithm on a Nios II softcore processor, with hardware acceleration. The project is composed of background analysis which details the main context of the project and details the problem to be answered in this report. Then, a design model study is proposed to enhance the analysis, design and implementation of the project. The system analysis and design and the motion detection algorithm analysis and design are successively given. Finally, the implementation of the proposed solution and the testing and experiments parts are detailed. The video capture and transmission are successfully implemented. Those parts are implemented in full hardware, using Verilog programming language. The motion detection algorithm implemented is a background subtraction algorithm. As the recording and storage blocks are not successfully implemented, frames stored on the desktop le system are used to test the algorithm. It is fully implemented in software, using ANSI-C programming language. Storage and recording parts are not implemented due to memory chip problems. As a conclusion, the optimization of video surveillance by using FPGA seems to be possible, but with a custom and optimized platform instead of a "standard one" (i.e. produced by a manufacturer). In facts, the memory chip of the selected board is an 8 MB SDRAM chip, while for this project two 256 MB SDRAM would have been better.
Publication date2008
Number of pages110
Publishing institutionAAU
ID: 14366239