The objective of the project is to develop, analyze and implement a frequency drift compensation algorithm for use in 3G wireless transceiver systems.

It is shown that frequency drift severely degrades the performance of 3G wireless communication systems, thus making the compensation algorithm needed.

Three algorithms are analyzed for their individual properties and one of these are chosen for implementation. This algorithm consists of a phase estimator and a phase jump detector, where the phase estimator averages the phase error of previous input in a filter structure and the phase jump detector removes phase ambiguities created by the phase estimator. The original algorithm is developed for BSPK but as 3G utilizes QPSK, making an extension necessary. The extended algorithm is then simulated and analyzed with respect to fixed point and complex number representation. Based on these simulation it is concluded that the performance converges towards the theoretical performance of QPSK without frequency drift.

The Complexity of the algorithm is found to determine a suitable platform for the implementation. The algorithm is also pipelined and the inherent parallelism of the algorithm exploited to minimize the execution time. The platform chosen is the Altera Cyclone 3 FPGA. A test system for finding the performance of the algorithm is implemented onto the FPGA along with the algorithm. The performance of the implemented algorithm is shown to closely resemble the performance of the MATLAB simulations of the algorithm. The developed algorithm is therefore considered working and suitable for prototype use in 3G transceiver systems.