Computational Considerations for Ultra-Reliable Low Latency Wireless Networks
Student thesis: Master thesis (including HD thesis)
- Alexander Korsvang Hagelskjær
4. term, Signal Processing and Computing, Master (Master Programme)
Industrial control networks have traditionally been implemented on wired connections due to latency and reliability constraints. Next-generation cellular networks include services with improvements in these areas, but the improvements are not sufficient for all targeted use cases. Wireless Isochronous Real Time communication (WIRT) is a newly proposed system that targets networked control systems with periodic transmissions and extreme latency and reliability requirements.
This work highlights considerations when implementing the WIRT physical layer. The system architecture is based on Orthogonal Frequency Division Multiplexing (OFDM) for Ultra-WideBand (UWB) spectrum. A prototype implementation is made. The implementation integrates UWB testing equipment, to serve as a testbed for further WIRT development. The implementation is used to estimate which parts of the transceiver introduce the highest latency. The minimum possible latency is determined and the computational complexity of each component is evaluated. Based on this evaluation, architectures for a latencyaccurate implementation are discussed.
The decoding of Error Correction Codes (ECCs) is found to be the largest single contributor to latency. Algorithmic alterations are made to reduce the minimum decoding latency to an acceptable level, along with other considerations required for implementation on a reconfigurable logic platform. In the end considerations and further work to prove the feasibility of the system are discussed.
This work highlights considerations when implementing the WIRT physical layer. The system architecture is based on Orthogonal Frequency Division Multiplexing (OFDM) for Ultra-WideBand (UWB) spectrum. A prototype implementation is made. The implementation integrates UWB testing equipment, to serve as a testbed for further WIRT development. The implementation is used to estimate which parts of the transceiver introduce the highest latency. The minimum possible latency is determined and the computational complexity of each component is evaluated. Based on this evaluation, architectures for a latencyaccurate implementation are discussed.
The decoding of Error Correction Codes (ECCs) is found to be the largest single contributor to latency. Algorithmic alterations are made to reduce the minimum decoding latency to an acceptable level, along with other considerations required for implementation on a reconfigurable logic platform. In the end considerations and further work to prove the feasibility of the system are discussed.
Language | English |
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Publication date | 6 Jun 2019 |
Number of pages | 73 |
External collaborator | LitePoint No Name vbn@aub.aau.dk Other |