A master thesis from Aalborg University
Dynamic Reconfiguration of Link Adaptation algorithms for a Multi Carrier System
Author(s)
Term
10. term
Publication year
2007
Submitted on
2007-06-07
Pages
95 pages
Abstract
The objective of this project is to analyze whether dynamic partial reconfiguration (PR) of an FPGA is feasible for Link Adaptation (LA) algorithms for an OFDM system such asWiMAX. Partial reconfiguration of an FPGA saves hardware area by virtue of its reusability. Previously two algorithms SRA and SAMPDA were implemented and a large difference in area usage was noted while providing the same performance at certain conditions. To exploit this property, partial reconfigurability of an FPGA is studied. A new methodology called ATtACk is proposed that helps to move systematically toward implementing a PR system. A step by step process is followed in three domains to finally assess implementation possibilities. A live setup is used to calculate the SNR which is used as the criteria for selecting an algorithm. Guidelines for PR are first studied. It is seen that the pin connections on the FPGA development board, architectural limitations of the FPGA and size of the hardware area requirement do not allow implementation of a complete PR system on the development board considered. Thus each portion of the design is separately implemented and these limitations are analyzed and further changes are proposed. Considerations regarding a practical reconfigurable LA are also discussed. Based on the limitations experienced and the algorithm to be implemented, it is concluded that a PR system for the two LA algorithms is possible provided that further architectural changes and algorithmic optimizations are performed.
The objective of this project is to analyze whether dynamic partial reconfiguration (PR) of an FPGA is feasible for Link Adaptation (LA) algorithms for an OFDM system such asWiMAX. Partial reconfiguration of an FPGA saves hardware area by virtue of its reusability. Previously two algorithms SRA and SAMPDA were implemented and a large difference in area usage was noted while providing the same performance at certain conditions. To exploit this property, partial reconfigurability of an FPGA is studied. A new methodology called ATtACk is proposed that helps to move systematically toward implementing a PR system. A step by step process is followed in three domains to finally assess implementation possibilities. A live setup is used to calculate the SNR which is used as the criteria for selecting an algorithm. Guidelines for PR are first studied. It is seen that the pin connections on the FPGA development board, architectural limitations of the FPGA and size of the hardware area requirement do not allow implementation of a complete PR system on the development board considered. Thus each portion of the design is separately implemented and these limitations are analyzed and further changes are proposed. Considerations regarding a practical reconfigurable LA are also discussed. Based on the limitations experienced and the algorithm to be implemented, it is concluded that a PR system for the two LA algorithms is possible provided that further architectural changes and algorithmic optimizations are performed.
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